1. Field of the Invention
The present invention relates to a printed circuit board and a method for manufacturing the same, and more particularly, to a printed circuit board capable of implementing high-density interlayer connection and a fine circuit by reducing a size of a via, and a method for manufacturing the same.
2. Description of the Related Art
In recent times, miniaturization and technology integration of electronic devices and products have been steadily developed due to advance of the electronic devices and products. In addition, various changes in a manufacturing process of a printed circuit board used in the electronic devices and products are also needed in response to miniaturization and technology integration.
A technical direction for a method for manufacturing a printed circuit board has been developed from a single-sided printed circuit board to a double-sided printed circuit board at an early stage and to a multilayer printed circuit board again. Especially, recently, in manufacturing a multilayer printed circuit board, a manufacturing method, which is called a build-up method, is being developed.
Meanwhile, in a manufacturing process of a printed circuit board, a process of forming various via holes such as an inner via hole (IVH), a blind via hole (BVH), and a plated through hole (PTH) for electrically connecting between a circuit pattern and an electronic element of each layer is needed. In the prior art, a printed circuit board is manufactured by forming a via hole in an insulator, plating the inside of the via hole to form a via, and forming a circuit pattern including a pad on a surface of the insulator when the via for interlayer electrical connection is formed.
However, in order to respond to a demand for high density and thinning of a printed circuit board, high-density interlayer connection and a fine circuit should be implemented by reducing the size of the pad and the via formed under the pad, but when forming a printed circuit board according to the prior art, there is a limitation in reducing the size of the via. That is, when simply reducing the size of the via, there is a difficulty in completely plating the via or processing the small via since an aspect ratio, a ratio of height to size (diameter) of the via, is increased.
In order to overcome this problem, a technology for reducing a size of a via without increasing an aspect ratio is needed. In the prior art, since a thin insulator should be used to uniformly maintain an aspect ratio, there is a limitation on the type of available substrates. Due to this, there is difficulty in developing various products.
Further, a lot of costs and efforts are needed to develop a technology of plating a via and a technology of processing a small via.